Programme

 

Detailed Programme

 

Oral Presentations: Instructions

Poster Presentations: Instructions & Template

 

Invited Speakers

 

Keynote: Future memory Process & Equipment
Kuntack Lee, Samsung, Korea
The presentation will cover the process difficulties and requirement of next generation memory including DRAM, NAND, Emerging Memory in terms of performance and productivity. 3D structure formation and inspection will be critical for future memory,andovercoming low productivity is also important.

1.4 - Applications for surface engineering using atomic layer etching 
Eric A. JosephIBM T.J. Watson Research Center, USA
Over the course of the past few years, the semiconductor industry has continued to invent and innovate profoundly to adhere to Moore’s Law and Dennard scaling. This ever continuing trend to shrink device sizes coupled with the advent of novel materials, multi-component materials or even nanoscale materials, is growing the need for the ultimate etch solution: etching with atomic layer precision. Atomic layer etching is a promising path to answer the processing demands of thin high mobility channel devices on the angstrom scale. Self-limiting reactions, discrete reaction & activation steps, or extremely low ion energy etch plasmas are some of the pathways being pursued for precise sub-nanometer material removal. In this presentation, the ability to achieve atomic layer etch precision is reviewed in detail for a variety of material sets and implementation methods. For a cyclic approach most similar to a reverse ALD scheme, the process window to achieve a truly self-limited atomic layer etch process is identified and the limitations as a function of controlling the adsorption step, the irradiation energy, and the reaction process are examined. Alternative approaches, including processes to enable pseudo-ALE precision, are then introduced and results from their application investigated. It is shown than by reaction chemistry control, plasma-surface interactions can be optimized such that selectivities of 1-2 monolayers could be realized.  

4.1 - Extended-nano fluidic devices and the unique liquid properties
Kazuma Mawatari, The University of Tokyo, Japan 
Recently, similar to semiconductor industry, microfluidic device is further downscaling to 10-100 nm space, which we call extended-nano space. Because the extended-nano space is a space to bridge isolated molecules and normal bulk fluid, new solution chemistry can be expected. However, it was difficult to investigate due to the ultra-small space. Our group developed fundamental technologies for the extended-nano fluidics such as nanofabrication and bonding for glass substrates, aL-fL pressure driven fluidic control, partial surface modification, and single molecule detection. Based on these technologies, many unique liquid properties were found such as viscosity increase, enhanced proton mobility, lower dielectric constant. In addition, the liquid property changes depended on channel size, channel shape, and kinds of liquid. New analytical and energy devices are created utilizing the unique properties in the extended-nano space. In this talk, fundamental technologies and unique liquid properties found in this space are mainly presented, which would have impact not only on chemistry and biology but also on semiconductor industry.

7.1 - Molecular simulation contribution to the characterization of process induced damages on porous low-k materials
Lucile BroussousSTMicroelectronics, France
Porous low-k materials used as insulator for interconnection levels in CMOS devices, are easily damaged during the patterning processes. Pore size characterization after material damage is challenging due to the chemical modification induced by the applied process. Numerical simulation of solvent adsorption on silica and functionalized silica surfaces was used to improve material pore size determination by ellipso-porosimetry, taking into account the modifications of surface/solvent interactions.

7.2 – Adventures and advances in selective deposition of dielectrics
David ThompsonApplied Materials, USA 
 

11.1 - Electrical characterization of as-processed semiconductor surfaces
Jerzy RuzylloPenn State University, USA 
The paper is concerned with electrical characterization of as-processed semiconductor surfaces and near-surface regions for the purpose of process development and monitoring. The “as-processed” surface is understood as the surface which between last process step such as chemical oxide etching and the measurement was not subject to any additional operations involving for instance thermal anneal/oxidation or contact deposition. The methods of electrical characterization based on Surface Photovoltage (SPV) and Photoconductance Decay (PCD) effects are discussed as being particularly conducive with the needs of as-processed semiconductor surface characterization. The former does not require a physical contact to the measured surface while the latter uses temporary probe contacts to the surface to perform the measurement.  In the discussion several examples concerned with surface charge measurements for the purpose of  surface cleaning monitoring and minority carrier lifetime measurements for the purpose of identification of the surface/near-surface defects  are presented to demonstrate merits of the proposed methodology.